Job Description: We are seeking a highly skilled DFT Engineer to join our dynamic team.
The successful candidate will be responsible for the design for test (DFT) implementation
in semiconductor designs, ensuring that products meet high quality and reliability
standards. This role offers the opportunity to work on cutting-edge semiconductor designs
in a collaborative and fast-paced environment.
Key Responsibilities:
- In depth knowledge of DFT concepts
- In depth knowledge and hands on experience in scan insertion, ATPG, coverage
analysis, Transition delay test coverage analysis - Expertise in test mode timing constraints definition, knowledge in providing timing
fixes/corrective actions for timing violations - Expertise in scripting languages such as perl, shell, etc.
- Experience in simulating test vectors
- Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass)
and ATPG tool like (TK, TetraMax) - Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a
plus - Ability to work in an international team, dynamic environment
- Ability to learn and adapt to new tools and methodologies.
- Ability to do multi-tasking & work on several high priority designs in parallel.
- Excellent problem solving skills
- Excellent communication and team work skills and good English is required
Benefits:
- Competitive salary and performance-based bonuses.
- Comprehensive benefits package, including health insurance, retirement plans, and
paid time off. - Opportunities for professional development and career growth.
- Collaborative and innovative work environment with state-of-the-art facilitie